The present invention relates to a semiconductor integrated circuit and a design method for the same, and more particularly, to circuit modifiability in the design stage.
In recent years, design rules of semiconductor integrated circuits have become finer and the semiconductor process technology has been more sophisticated. In this situation, the cost of masks used in a semiconductor process has risen. At the time of circuit modification, therefore, it has been requested to reduce the number of layers to be modified to a minimum so as to minimize the number of masks to be modified. At the time of modification for a clock system, it has been additionally requested to suppress a skew variation that may occur with the modification.
There are known methods for circuit modification in which an integrated circuit is provided in advance with a cell unnecessary for its original function (hereinafter, such a cell is called a dummy cell) in preparation for circuit modification. In the following two methods, a flipflop (FF) is used as a dummy cell for circuit modification (see Japanese Laid-Open Patent Publication No. 2005-322694, for example).
FIG. 13 is a circuit diagram of an example of a semiconductor integrated circuit using dummy cells. The circuit of FIG. 13 has dummy cells 34. Clock tree synthesis (CTS) is executed in advance in the state of having the dummy cells 34 connected in place of FF cells 35. Once a circuit modification involving addition of a FF cell becomes necessary, a dummy cell 34 is replaced with a FF cell 35.
The CTS as used herein refers to placing buffers at optimal positions in a buffer tree so that clock skew be minimized in the state of including dummy cells as well as flipflops required for the original function.
FIG. 14 is a circuit diagram of another example of a semiconductor integrated circuit using dummy cells. In FIG. 14, dummy FFs 37 are already placed at positions near dummy cells 36. Once a circuit modification involving addition of a dummy FF becomes necessary, an interconnect to a dummy cell 36 located near the position at which the circuit modification is necessary is cut off, and a dummy FF 37 located near the dummy cell 36 is connected in place of the disconnected dummy cell 36.
The semiconductor integrated circuits described above have the following problems. In the case of FIG. 13, which requires cell replacement, both a diffusion layer (lower layer) and an interconnect layer (upper layer) must be changed. This is therefore greatly disadvantageous in the aspects of cost (mask cost, etc.) and the development time.
In the case of FIG. 14, which requires rerouting of interconnects, a difference arises between the length of an interconnect to a dummy cell and the length of an interconnect to a reconnected dummy FF cell, and this may adversely affect clock skew. Also, since clock routing is often made in consideration of signal integrity, there are concerns that congestion may occur due to the rerouting and that signal integrity measures for the modified interconnect may be insufficient.